Efficient VLSI Parallel Implementation for LDPC Decoder

Iterative decoding of Low Density Parity Check (LDPC) codes using the Parity Likelihood Ratio (PLR) algorithm have been proved to be more efficient compared to conventional Sum Product Algorithm (SPA). However, the nature of PLR algorithm tends to put numerious pieces of data to this decoder and perform computation intensive operations, which is a major challenge for building a practical real-time LDPC decoder. In this paper, we employ extrinsic information clipping and calculation step merging techniques, which are used in modified sequential architecture, into the parallel implementation of LDPC decoder. The proposed parallel architecture decreases the decoding latency without increases the memory storage compared to existing modified sequential design. Simulation results show that the proposed architecture results in time savings of up to 96.12% and 37.94% over conventional direct sequential implementation and modified sequential design respectively. Key-Words: LDPC codes, parallel architecture, VLSI implementation, PLR algorithm